Traditional and Truncation schemes for Different Multiplier

A rapid and proficient in power requirement multiplier is always vital in electronics industry like DSP, image processing and ALU in microprocessors. Multiplier is such an imperative block w ith respect to power consumption and area occupied in the system. In order to meet the demand for high speed, various parallel array multiplication algorithms have been proposed by a number of authors. The array multipliers use a large amount of hardware, consequently consuming a large amount of power. One of the methods for multiplication is based on Indian Vedic mathematics. The total Vedic mathematics is based on sixteen sutras (word formulae) and manifests a merged structure of mathematics. The parallel multipliers for example radix 2 and radix 4 booth multiplier does the computations using less number of adders and less number of iterative steps that results in, they occupy less space to that of serial multiplier. Truncated multipliers offer noteworthy enhancements in area, delay, and power. Truncated multiplication provides different method for reducing the power dissipation and area of rounded parallel multipliers in DSP systems. Since in a truncated multiplier the x less significant bits of the full-width product are discarded thus partial products are removed and replaced by a suitable compensation equations, match the accuracy with hardware cost. A pseudo-carry compensation truncation (PCT) scheme, it is for the multiplexer based array multiplier, which yields less average error among existing truncation methods. After studying many research papers it’s found that some of the schemes for multiplier are suitable because their own uniqueness of multiplication. Such schemes are listed in this paper for example the different truncation schemes like constant-correction truncation (CCT), variable -correction truncation (VCT), pseudo-carry compensation truncation (PCT) are most suitable for truncated multiplier.